Apr 13 — Apr 15, 2021 Virtual

Hybrid Metrology Solutions for Monitoring Microbump Process 20µm Pitch and Less for 2.5D and 3D Integration

Priya Mukundhan

Priya Mukundhan

Presentation at 17th Annual Device Packaging Conference
9:00am — 5:00pm

High performance computing applications and data-intensive workloads like gaming, machine learning and artificial intelligence require lower latency, lower power consumption and higher interconnect speeds. Memory packaging is a key enabler as it brings DRAM and logic closer together through various integration schemes. High Bandwidth memory (HBM) that stacks multiple DRAM devices in a 4-high, 8-high, 12-high configurations provide higher bandwidth and better efficiency. HBM3 that is in R&D is expected to have even faster performance but would still be niche to high-end applications because of the expensive process. Microbumps are integral and critical to achieving the die-to-die and die-to-wafer stacking. Solder based, fine pitch, micro-bump connections are preferred mainly due to lower bonding temperature and time, which allows for a high throughput thermo-compression bonding compared with Cu-to-Cu bonding. Typical solder height is 15-30µm in Cu pillars and it is expected to scale down to less than 10µm in 20µm pitch interconnections. However, with reducing bump dimensions, several critical reliability issues arise. Studies have shown that for a 20?m microbump the current density can reach values that are significantly higher than the threshold value of Sn electro migration (EM) and the failure mechanism in microbumps are different from traditional flip chip bump.

Picosecond laser acoustics (PLA) is used in front end wafer fabs for measuring thickness of multi-layer stacks. Adoption in advanced packaging is being driven by the need for more stringent process control requirements in logic to logic and logic to DRAM integration. Process window for some of the advanced micro bump stacks (20µm and below) is shrinking rapidly and the metrology requirement for measurement of thickness of the multi-layer pillar stacks is ~ 3 sigma < 1% for each of the layers. When the stacks contain repeating layers of the same metal as in Cu/Ni/CuSnAg, X-ray metrology techniques suffer from inability to differentiate the two Cu layers. Also, X-ray- induced damage to DRAM devices and impact to yield is a real concern as the cost per unit of stacking the DRAM die in HBM cubes in 8-high, 12-high configurations that are significantly high. By modifying the optics design, we have extended the capability of the PLA to be able to measure thick as-plated pillar bumps. Measuring the pillars prior to reflow provides not only insight to the individual layer thickness variations but also provides information a day or two earlier which is relevant during process development. Results show good agreement with cross-section SEM. Cross wafer measurements of multiple pillars as well as line scans across select pillar bumps were performed to map within bump and within wafer uniformity. This information is useful during R&D to obtain information on thickness variation as well an opportunity to study the ageing of pillars and formation of intermetallic compounds. In high volume manufacturing environments, post re-flow microbump characterization is performed using the metrology sensor options that are integrated as part of the automated optical inspection tools. In this paper, we will review the hybrid metrology approach and analysis of how data from these measurements can be complementary and how they can be leveraged in the pillar bump process flow.